The present invention relates to a logic circuitry-implemented bus buffer. Particularly, this invention relates to a bus buffer having several buffers provided at least at input and output stages with internal circuitry interposed therebetween.
With recent dramatic development of information-processing technology, several types of bus buffers haven been introduced, which are interposed between several data buses, for relaying data signals transferred through the data buses. Data transferred through a bus at one side of the bus buffer and that through another bus at the other side of the bus buffer may be or may not be sent at the same transfer speed. Moreover, data transfer via the bus buffer may be one-way or two-way transfer between the buses at one and the other sides of the bus buffer.
Applications such as Personal Digital Assistant (abbreviated to PDA hereinafter) include many bus (signal) lines for data transfer between a central processing unit (abbreviated to CPU hereinafter) in logic-circuit system and peripheral devices connected to busses in tree structure. Peripheral devices applicable to this type of application are classified into a device group (called high-speed accessible device group) including devices such as synchronous dynamic random access memories (abbreviated to SDRAM hereinafter) and another device group (called low-speed accessible device group) including devices accessible at low speed such as connectors for connection of external peripheral devices, and nonvolatile memories.
When all of the peripheral devices are driven by CPU, not only the high-speed accessible device group but also the low-speed accessible device group are driven, thus increasing power consumption which depends on device input capacity, etc. Provided for solving such a problem are usually high-speed buses for high-speed access use and low-speed buses for low-speed access use, and also bus buffers for connecting the high- and low-speed buses.
It is a well-known power-saving measurement for hand-held devices to interpose a bus buffer between high- and low-speed buses for data transfer like explained above for lowering total power consumption in application such as PDA. This measurement deactivates the low-speed accessible device group through a bus buffer while the high-speed accessible devices such as SDRAMs are being accessed, thus achieving low power consumption.
FIG. 41 is a block diagram showing the internal configuration of a well-known bus buffer 10 to which off-the-shelf bus buffer devices are applicable. The bus buffer 10 shown in FIG. 41 is equipped with a controller 11 for generating several control signals of different logic levels in response to an input/output command signal *OE from CPU and a direction-indicating signal DIR, terminals A1 to An for data transfer with CPU through high-speed accessing buses, terminals B1 to Bn for data transfer with a low-speed accessible device group through low-speed accessing buses, and several operators 12 for logic operation with specific internal circuitry provided between the terminals A1 to An and B1 to Bn.
The sign xe2x80x9c*xe2x80x9d indicates a logic-level-inverted signal. For example, the signal *OE as the input/output command signal is a signal whose logic level is an inverted-version of a signal OE. The sign OE is an abbreviation of Output Enable. The sign xe2x80x9cnxe2x80x9d in the terminals A1 to An and B1 to Bn is a positive integer.
Disclosed below for the operators 12 in FIG. 41 is only for the operator 12 provided between the terminals A1 and B1 because all of the operators 12 have the same circuit configuration.
The operator 12 is equipped with a first-directional-signal processor including a first input buffer 13 made up of an inverter INV1 for accepting a signal from the terminal A1; an A/B-internal circuit 14 made up of an inverter INV2 for signal processing in a direction from the terminals A1 to B1 (called a first direction); and a first output buffer 15 for outputting a signal from the A/B-internal circuit 14 to the terminal B1, having a NAND-logic circuit NAND1, a NOR-logic circuit NOR1, a P-channel transistor P1, and an N-channel transistor N1.
The operator 12 is equipped further with a second-directional-signal processor including a second input buffer 16 made up of an inverter INV3 for accepting a signal from the terminal B1; a B/A-internal circuit 17 made up of an inverter INV4 for signal processing in a direction from the terminals B1 to A1 (called a second direction); and a second output buffer 18 for outputting a signal from the B/A-internal circuit 17 to the terminal A1, having a NAND-logic circuit NAND2, a NOR-logic circuit NOR2, a P-channel transistor P2, and an N-channel transistor N2.
All of the terminals A1 to An and B1 to Bn are input and also output terminals. Input via a terminal *OE is the input/output command signal *OE for switching the bus buffer 10 between a signal-output mode and a high-impedance state at the input and output terminals. Input via a terminal DIR is the direction-indicating signal DIR for switching the bus buffer 10 for input/output directions. Disclosed next is an operation of the bus buffer 10 shown in FIG. 41.
The controller 11 in FIG. 41 generates signals *AG, AG, *BG and BG in response to the input/output command signal *OE and the direction-indicating signal DIR input via the terminals *OE and DIR, respectively. It is assumed that the signal *OE is at a low level whereas the signal DIR at a high level so that a signal is allowed to be input via the terminal A1 and output via the terminal B1. The signal input via the terminal A1 is then transferred to the transistors P1 and N1 via the inverter INV1 of the first input buffer 13, the inverter INV2 of the A/B internal circuit 14, and NAND1 and NOR1 of the first output buffer 15, and output via the terminal B1.
The signal at the terminal B1 is not only output but supplied to one of two terminals of NAND2 and also NOR2 of the second output buffer 12 via INV3 of the second input buffer 16 and INV4 of the B/A internal circuit 17 from a node connected to the terminal B1, thus these logic circuits are inevitably activated. A gate signal to the transistor P2 is, however, set at a high level whereas that to the transistor N2 is set at a low high level due to a low level for the signal BG whereas a high level for the signal *BG. The transistors P2 and N2 of the second output buffer 18 are thus turned off, so that no signals will be output via the terminal A1.
The bus buffer 10, however, consumes power due to unwanted currents passing through the activated logic circuits. TABLE 1 in FIG. 42 shows logic levels at the terminals A1 and B1 and modes of the respective circuits. It is indicated in TABLE 1 that the second-directional-signal processor is in operation even when a signal is transferred in the first direction whereas the first-directional-signal processor is in operation even when a signal is transferred in the second direction. Moreover, even when the first and second output buffers 15 and 18 are out of operation, the NAND- and NOR-logic circuits at the anterior stage to these output buffers are performing logical operations.
Furthermore, signals input to both terminals A1 and B1 simultaneously activate all of the first input buffer 13, the A/B-internal circuit 14, the second input buffer 16, and the B/A-internal circuit 17, thus causing high power consumption. This will happen even when the terminals A1 and B1 are in the high-impedance state (*OE=H), irrespective of the logic level of the signal DIR.
A first bus-hold circuit 19a and a second bus-hold circuit 19b enclosed in a dot-line block are provided for solving the problem discussed above. The bus-hold circuit 19a is made up of two inverters connected between the first output buffer 15 and the terminal B1. The bus-hold circuit 19b is made up of two inverters connected between the second output buffer 18 and the terminal A1. The two inverters for both bus-hold circuits 19a and 19b are cross-coupled to each other.
Disclosed with respect to TABLE 2 in FIG. 43 is an operation of the bus buffer 10 equipped with the first and the second bus-hold circuits 19a and 19b. TABLE 2 in FIG. 43 shows logic levels at the terminals and modes of the respective circuits. TABLE 2 is identical with TABLE 1 except the first and the second bus-hold circuits 19a and 19b. The bus-hold circuits 19a and 19b should be in operation only when the input/output command signal *OE is at a high level. It is indicated in TABLE 2, however, that the bus-hold circuits 19a and 19b are both in operation even when the input/output command signal *OE is at a low level. Signal transfer from the terminals A1 to B1 while the bus-hold circuits 19a and 19b are in operation causes current consumption even if there is no need of bus holding.
As discussed above, such bus-hold circuits for protecting terminals, via which signals are to be input in specific directions, from being in high-impedance state are of no use for the bus buffer. Because all circuits in the bus buffer will be inevitably in operation, thus causing unnecessary power consumption, against the aim of low power consumption in applications such as PDA. Such an arrangement thus has a problem of inefficient reduction in power consumption.
A purpose of the present invention is to provide a bus buffer having logic circuitry with less unnecessary power consumption by holding input to input buffers at a certain level, thus achieving further low power consumption.
A bus buffer having logic circuitry according to the first aspect of the present invention includes: a controller, provided between a plurality of two-way data buses through which at least one data signal is transferred, to generate a plurality of different control signals based on an input/output command signal instructing input/output of the data signal and a direction-indicating signal indicating a direction in which the data signal is to be transferred; a first terminal via which a first-directional signal to be transferred from a first bus side to a second bus side is input whereas a second-directional signal to be transferred from the second bus side to the first bus side is output; a second terminal via which the first-directional signal is output whereas the second-directional signal is input; a first-directional signal processor, provided between the first and second terminals, having a first input buffer, a first internal circuit and a first output buffer; and a second-directional signal processor, provided between the second and first terminals, having a second input buffer, a second internal circuit and a second output buffer, wherein the first input buffer has a first input holder to disactivate the first internal circuit and the first output buffer by using at least one of the control signals in accordance with states of the input/output command signal and the direction-indicating signal, and the second input buffer has a second input holder to disactivate the second internal circuit and the second output buffer by using the at least one control signal in accordance with the states.
A bus buffer having logic circuitry according o the second aspect of the present invention includes: a controller, provided between a plurality of one-way data buses through which at least one data signal is transferred, to generate a plurality of different control signals based on an input/output command signal instructing input/output of the data signal; an input terminal via which a one-way signal to be transferred from a first bus side is input; an input buffer connected to the input terminal; an internal circuit connected to the input buffer; an output buffer connected to the internal circuit; an output terminal via which an output signal of the output buffer is output to a second bus side, wherein the input buffer has a logic circuitry to perform a logic operation by using one of the control signals having a specific level and the data signal input via the input terminal, to activate the internal circuit and the output buffer, thus outputting a result signal via the output terminal, whereas to disactivate the internal circuit and the output buffer when the data signal is not input via the input terminal.